`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/11/19 14:52:20
// Design Name: 
// Module Name: test_4bit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module test_4bit;
 
	// Inputs
	reg [3:0] a1;
	reg [3:0] a2;
	reg choose;
	reg clk;
 
	// Outputs
	wire [7:0] y;
	wire [7:0] s;
	wire [4:0] a3;
 
	// Instantiate the Unit Under Test (UUT)
	add_jian_4 uut (
		.a1(a1), 
		.a2(a2), 
		.y(y), 
		.s(s), 
		.choose(choose), 
		.clk(clk), 
		.a3(a3)
	);
always #10 clk=~clk;
 
	initial begin
		// Initialize Inputs
		
		//12+1=13
		a1 = 1;
		a2 = 12;
		choose = 0;
		clk = 0;
		#1000;// Wait 100 ns for global reset to finish
        
		  //12+12=24
		a1 = 12;
		a2 = 12;
		choose = 0;
		clk = 0;
		#1000;// Wait 100 ns for global reset to finish
		
		//12-1=11
		a1 = 12;
		a2 = 1;
		choose = 1;
		#1000;// Wait 100 ns for global reset to finish
		
		//12-10=2
	   a1 = 12;
		a2 = 10;
		choose = 1;
		#1000;// Wait 100 ns for global reset to finish
		
		//15+15=30
	   a1 = 15;
		a2 = 15;
		choose = 0;
		#1000;// Wait 100 ns for global reset to finish
		
		//15-10=5
	   a1 = 15;
		a2 = 10;
		choose = 1;
 
	end
      
endmodule

